1. Field of the Invention
This invention relates generally to impedance buffers for isolating a low-current source from high-current loads and, more specifically, to an impedance buffer circuit suited for accurate monolithic sample-and-hold device applications.
2. Description of the Related Art
A typical data-acquisition system receives signals from a number of different sources and transmits these signals in suitable form to a communication channel or computer. A multiplexer selects each signal in sequence and the analog information is then converted into a constant sample voltage over a gating-time interval by means of a sample-and-hold system. The constant output of the sample-and-hold system may then be converted to a digital signal, using analog-to-digital converter techniques, for digital transmission. A sample-and-hold circuit in its simplest form is merely a switch in Series with a charge storage device such as capacitor (FIG. 3A). The switch is closed during the sample interval to permit the analog signal voltage to charge the capacitor, which then retains the charge necessary to provide a constant sample-voltage output signal.
In such a sample-and-hold circuit, as in many other circuits, it is necessary to quickly drive the capacitive load to the desired voltage. Ideally, a perfect step voltage source (e.g.: FIG. 3B) would drive a capacitor (e.g.: C.sub.LOAD in FIG. 3A) to its fully-charged state instantaneously (such as illustrated in FIG. 3C). In the real world, perfect step voltage sources do not exist. Every real voltage source exhibits finite output impedance, slew rate limits and other sources of error. When a signal supplied from a first driving circuit is insufficient to meet the demands of a second loading circuit, the performance of both is degraded.
Practitioners in the art have introduced several solutions to this problem over the years. Two popular circuits for driving capacitive loads are the emitter-follower amplifier and the differential amplifier. Each of these well-known circuits operates as an impedance buffer placed between the output of a first driving circuit and the input of a second loading circuit. The impedance buffer has a high input impedance that draws little current from the first driving circuit and a low output impedance that supplies a high current to the second loading circuit without affecting first driving circuit performance. Also, an impedance buffer may act as a voltage follower that introduces predetermined changes to the voltage level of the signal transmitted between the circuits.
FIG. 4A shows a simple emitter-follower amplifier well-known in the art for driving capacitive loads. Emitter-follower amplifiers are extremely fast because they offer low output impedance and high output current capacity. Emitter followers are simple in design and implementation and relatively inexpensive. Such amplifiers possess a fixed voltage gain of nearly unity, making them attractive candidates for driving capacitive loads.
However, the emitter-follower amplifier also has significant disadvantages. The output voltage waveform in FIG. 4C exhibits the inherent voltage offset from the input voltage (compare FIG. 4B). Also, the single-ended emitter follower shown in FIG. 4A does not drive the load equally in both rising and falling directions. The NPN Bipolar Junction Transistor (BJT) Q1 shown in FIG. 4A drives the output voltage V.sub.OUT upward rapidly but does not bring it down as quickly. The circuit may drive the load faster upwards or downwards, depending on whether NPN or PNP BJTs are used.
FIG. 5C shows this characteristic for the dual NPN BJT emitter-follower amplifier of FIG. 5A driven by the square wave input of FIG. 5B. FIG. 5C shows that the voltage on capacitor C.sub.LOAD quickly follows the rising edge of the input signal with the characteristic offset, but is slew rate limited on the following edge because of the limited bias current I.sub.BIAS . This slew rate problem can be reduced by increasing the V.sub.bias on transistor Q2 to increase the bias current level but this results in higher power dissipation.
FIG. 6A shows a complementary NPN-PNP BJT emitter-follower configuration, which is a solution to the slew rate problem alternative to increasing the bias current. In FIG. 6A, the PNP BJT Q2 is added in series with the NPN BJT Q1 from FIG. 4A. However, as seen in FIG. 6C, this solution introduces a second voltage offset to the falling edge signal, further distorting the initial input signal of FIG. 6B. Even so, the circuit of FIG. 6A is favored in the art. For instance, Jacob Millman (Microelectronics: Digital and Analog Circuits and Systems, "Sample-and-Hold Systems", pp 596-599, McGraw-Hill, Inc., New York, 1979) discusses the improved sample-and-hold configuration shown in FIG. 2 herein. The transistors Q1 and Q2 form an external complementary emitter-follower circuit between the sampling switch Q3 and the storage capacitor C to increase the current available for charging capacitor C.
The differential amplifier is also a well-known method for driving capacitive loads. FIG. 7A shows a typical differential amplifier used in the art for driving capacitive loads. The differential amplifier avoids the voltage offset problems seen in FIGS. 4C, 5C and 6C for typical emitter-follower amplifier circuits. The differential amplifier also reduces other nonlinearities by employing negative feedback. However, the differential amplifier exhibits the additional undesirable characteristics of slew rate limiting, overshoot, ripple and timing delays. These problems are characteristic of any feedback amplifier system with negative feedback such as the differential amplifier and are illustrated in the output waveform shown in FIG. 7C.
Although step inputs (FIG. 7B) to capacitive loads generally result in overshoot and ringing or ramping at too-slow slew rates, proper amplifier design can optimize the output voltage response (FIG. 7C) for selected applications. For instance, in U.S. Pat. No. 4,389,579, Marc T. Stein discloses a sample-and-hold circuit employing a cascoded amplifier coupled to the capacitive load for charging and discharging the capacitor. Also, in U.S. Pat. No. 4,542,305, Robert A. Blauschild discloses the impedance buffer shown in FIG. 1, which is based on a differential amplifier configuration. Blauschild includes a resistor coupled between the base and collector of an intermediate transistor to reduce output settling time. Note that Blauschild combines a differential amplifier consisting of transistors Q1 and Q2 with an emitter-follower amplifier that uses transistor Q3 at the output. However, Blauschild neither teaches nor considers use of an emitter-follow amplifier in parallel with his differential amplifier. In fact, useful application of such a parallel combination of amplifiers is heretofore unknown in the art.
There is a clearly-felt need in the art to provide effective impedance buffering between driving circuits having limited current driving capacity and driven circuits having very low impedance, such as an uncharged load capacitor. The related unresolved problems and deficiencies are clearly felt in the art and are solved by this invention in the manner described below.